[AMDGPU][Disassembler] Use target feature for .amdhsa_reserve_xnack_mask instead of hard code zero
#161771
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@llvm/pr-subscribers-backend-amdgpu Author: Shilei Tian (shiltian) ChangesThere is no test change at this moment because we don't have a target that has this feature by default yet. Full diff: https://github.com/llvm/llvm-project/pull/161771.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 2d5ae29c1037c..3d86e41e9e1b7 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -2303,7 +2303,12 @@ Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(
KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
if (!hasArchitectedFlatScratch())
KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
- KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n';
+ bool ReservedXnackMask = STI.hasFeature(AMDGPU::FeatureXNACK);
+#ifndef NDEBUG
+ assert(!ReservedXnackMask || STI.hasFeature(AMDGPU::FeatureSupportsXNACK));
+#endif
+ KdStream << Indent << ".amdhsa_reserve_xnack_mask " << ReservedXnackMask
+ << '\n';
KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_PRIORITY);
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rampitec
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Oct 3, 2025
…mask` instead of hard code zero There is no test change at this moment because we don't have a target that has this feature by default yet.
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/116/builds/19220 Here is the relevant piece of the build log for the reference |
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…mask` instead of hard code zero (llvm#161771) There is no test change at this moment because we don't have a target that has this feature by default yet.
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There is no test change at this moment because we don't have a target that has this feature by default yet.